View MCF5253_1926351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? freescale semiconductor, inc., 2007. all rights reserved. freescale semiconductor data sheet: technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: MCF5253ds rev. 2, 04/2007 MCF5253 package information mapbga?225 ordering information: see table 1 on page 2 1 introduction this document provides an overview of the MCF5253 coldfire processor and gene ral descriptions of the MCF5253 features and modul es. also provided are electrical specifications, pi n assignments, and package diagrams for MCF5253 coldfire ? processor. for functional characteristics, refer to the MCF5253 reference manua l (MCF5253rm). the MCF5253 is a general purpose system controller with over 125 dhrystone 2.1 mips @ 140 mhz performance. the integrated peripherals and emac allow the MCF5253 to repl ace both the microcontroller and the dsp in certain applic ations. most peripheral pins can also be remapped as general purpose i/o pins. low power features incl ude flexible pll (with power-down mode) with dynamic clock switching, a hardwired cd rom decoder, advanced 0.13 m cmos process technology, 1.2 v core power supply, and on-chip 128k-byte sram. MCF5253 coldfire ? microprocessor data sheet 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 orderable part numbers . . . . . . . . . . . . . . 2 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . 3 2 functional description . . . . . . . . . . . . . . . . . . . 4 2.1 version 2 coldfire core . . . . . . . . . . . . . . . 4 2.2 module inventory . . . . . . . . . . . . . . . . . . . . 4 3 signal description . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical specifications . . . . . . . . . . . . . . . . . 11 4.1 sdram bus timing . . . . . . . . . . . . . . . . . 14 4.2 spdif timing . . . . . . . . . . . . . . . . . . . . . . 15 4.3 serial audio interface timing . . . . . . . . . . 16 4.4 ddata/pst/pstclk debug interface . . 16 4.5 bdm and jtag timing . . . . . . . . . . . . . . 16 5 package information and pinout . . . . . . . . . . 18 5.1 pin assignment . . . . . . . . . . . . . . . . . . . . 18 5.2 package drawing . . . . . . . . . . . . . . . . . . . 24 6 product documentation . . . . . . . . . . . . . . . . . 31 6.1 revision history . . . . . . . . . . . . . . . . . . . . 31
introduction MCF5253 coldfire processor data sheet: technical data, rev. 2 2 freescale semiconductor for additional information regarding softwa re drivers and applications, refer to http://www.freesca le.com/coldfire . 1.1 orderable part numbers table 1 lists the orderable part numbers for the MCF5253 processor. table 1. orderable part numbers orderable part number maximum clock frequency package type operating temperature range part status MCF5253vm140 140 mhz 2 25 mapbga -20 to +70 c lead free
introduction MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 3 1.2 block diagram figure 1 illustrates the functional block diagram of the MCF5253 processor. figure 1. MCF5253 block diagram debug module with jtag coldfire cf2 core 140 mhz kram1 kram0 instruction cache 5x08 dma 5x08 arbiter 2x flexcan controller clock pll xtal oscillator real-time clock interrupt controller 8k 64k 64k ?backdoor? interface translator 16 kbyte sram spi interface audio interfaces ad logic arb dma memory stick/sd interface usb 2.0 otg controller ata controller timer 5x08 interrupt e-bus sdram interface e-bus i 2 c uart (3) smartmedia timer pins i 2 c pins uart pins mux sdram sram ide bufenb1 spi pins audio interface pins ad in pins ide _ dior ide _ diow ide _i ordy flashmedia pins usb analog usb xtal pins ata pins usb xtal oscillator usb phy standard coldfire peripheral blocks bufenb 2 flexcan pins crin/crout pins rtc pins
functional description MCF5253 coldfire processor data sheet: technical data, rev. 2 4 freescale semiconductor 2 functional description 2.1 version 2 coldfire core the version 2 coldfire (cf2 ) core consists of two independent, dec oupled pipeline struct ures to maximize performance while minimizing core size. the instructi on fetch pipeline (ifp) is a two-stage pipeline for prefetching instructions. the prefet ched instruction stream is then gated into the two-stage operand execution pipeline (oep), which d ecodes the instruction, fetches the required operands, and then executes the required function. 2.2 module inventory table 2 shows an alphabetical listing of the modules in the processor. table 2. digital and analog modules block mnemonic block name functional grouping brief description ata advanced technology attachment controller connectivity peripheral the ata block is an at attachment host interface. its main use is to interface with ide hard disc drives and atapi optical disc drives. adc battery level/keypad analog/digital converter analog input the six-channel adc is based on the sigma-delta concept with 12-bit resolution. both the analog comparator and digital sections are integrated in the MCF5253. ab audio bus audio interface the audio interfaces connect to an internal bus that carries all audio data. each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. aim audio interface audio interface the audio interface module provides the necessary input and output features to receive and transmit digital audio signals over serial audio interfaces (iis/eiaj) and over digital audio interfaces (iec958). brom bootloader boot rom the MCF5253 incorporat es a rom bootloader, which enables booting from uart, i2c, spi, or ide devices. flexcan twin controller area network 2.0b communication unit connectivity peripheral the flexcan module is a full implem entation of the bosch can protocol specification 2.0b, which supports both standard and extended message frames. csm chip select module connectivity peripheral three programmable chip-select outputs (cs0 /cs4 , cs1 , and cs2 ) provide signals that enable glueless connection to external memory and peripheral circuits. dmac direct memory access controller module connectivity peripheral there are four fully programmable dma channels for quick data transfer. emac enhanced multiply accumulate module core the integrated emac unit provides a common set of dsp operations and enhances the integer multiply instructions in the coldfire architecture. mbus memory bus interface bus operation the bus interface controller transfers data between the coldfire core or dma and memory, peripherals, or other devices on the external bus. mmc/sd multimedia card/secure digital interface flash memory card interface the interface is sony? memory stick?, securedigital, and multi-media card compatible. note: the sony memory interface does not support sony magicgate?.
functional description MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 5 gpio general purpose i/o interface system integration gpio signals are multiplexed with various other signals. gpt general timer module timer peripheral the timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer. ide integrated drive electronics connectivity peripheral the ide hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent sdram and flash accesses from propagating to the ide bus. inc instruction cache core t he instruction cache improves system performance by providing cached instructions to the execution unit in a single clock cycle. i 2 c inter ic communication module connectivity peripheral the two-wire i 2 c bus interfaces, compliant with the philips i 2 c bus standard, are bidirectional serial buses that exchange data between devices. sram internal 128-kb sram internal memory the 128-kbyte on-chip sram is split over two banks, sram0 (64k) and sram1 (64k). it provides single cloc k-cycle access for the coldfire core. lin internal voltage regulator linear regulator an internal 1.2 v regulator is used to supply the cpu and pll sections of the MCF5253, reducing the number of external components required and allowing operation from a single supply rail, typically 3.3 volts. jtag joint test action group test and debug to help with system diagnostics an d manufacturing testing, the MCF5253 includes dedicated user-accessible test logic that complies with the ieee 1149.1a standard for boundary scan testability, often referred to as joint test action group, or jtag. qspi queued serial peripheral interface connectivity interface the qspi module provides a serial peripheral interface with queued transfer capability. rtc real-time clock timer peripheral the rtc is a clock that keeps track of the current time even if the clock is turned off. bdm background debug interface test and debug a background-debug mode (bdm) interface provides system debug. sdramc synchronous dram memory controller peripheral interface the sdram controller provides a gl ueless interface for one bank of sdram, and can address up to 32mb. the controller supports a 16-bit data bus. the controller operates in page mode, non-page mode, and burst-page mode and supports sdrams. sim system integration module system integration the sim provides overall control of the internal and external buses and serves as the interface between the coldfire core and the internal peripherals or external devices. the sim is responsible for the two interrupt controllers (setting priorities and levels). and it also configures the gpio ports. pll system oscillator and phase lock loop system clocking the oscillator operates from an external crystal connected across crin and crout. the circuit can also operate from an external clock connected to crin. the on-chip prog rammable pll, which generates the processor clock, allows the use of almost any low frequency external clock (5?35 mhz). table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description
signal description MCF5253 coldfire processor data sheet: technical data, rev. 2 6 freescale semiconductor 3 signal description this chapter describes the MCF5253 input and output signals. the signal descriptions as shown in table 3 are grouped according to rele vant functionality. for additional si gnal information, s ee ?chapter 2, signal description? in the MCF5253 reference manual. uart universal asynchronous receiver /transmitter module connectivity peripheral three uarts handle asynchronous serial communication. usbotg usb 2.0 high-speed on-the-go connectivity peripheral the usb module is used for communication to a pc or communication to slave devices; for example, to download data from a hard disc player to a flash player, and to other devices. table 3. MCF5253 signal index signal name mnemonic function input/ output reset state address a[24:1] a[23]/gpo54 24 address lines?address 23 is multiplexed with gpo54 and address 24 is multiplexed with a20 (sdram access only). out x read-write control rw bus write enable?indicates if read or write cycle in progress. out h output enable oe output enable for asynchronous memories connected to chip selects out negated data d[31:16] data bus used to transfer word data in/out hi-z synchronous row address strobe sdras /gpio59 row address strobe for external sdram out negated synchronous column address strobe sdcas /gpio39 column address strobe for external sdram out negated sdram write enable sdwe /gpio38 write enable for external sdram out negated sdram upper byte enable sdudqm /gpo53 upper byte enable?indicates during write cycle if high byte is written. out ? sdram lower byte enable sdldqm /gpo52 lower byte enable?indicates during write cycle if low byte is written. out ? sdram chip selects sd_cs0 /gpio60 sdram chip select in/out negated sdram clock enable bclke/gpio63 sdram clock enable out ? system clock bclk/gpio40 sdram clock output in/out ? table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description
signal description MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 7 isa bus read strobe ide _d ior /gpio31 (cs2 ) 1 isa bus read strobe and 1 isa bus write strobe?allow connection of an independent isa bus peripheral, such as an ide slave device. in/out ? isa bus write strobe ide _d iow /gpio32 (cs2 ) in/out ? isa bus wait signal ide _i ordy /gpio33 isa bus wait line available for both busses in/out ? chip selects[2:0] cs0 /cs4 cs1 /qspics3/gpio28 chip selects bits 2 through 0? enable peripherals at programmed addresses. c s 0 provides boot rom selection. out in/out negated buffer enable 1 bufenb1 /gpio29 two programmable buffer enables?allow seamless steering of external buffers to split data and address bus in sections. in/out ? buffer enable 2 bufenb2 /gpio30 in/out ? transfer acknowledge ta /gpio12 transfer acknowledge signal. in/out ? wake up wake u p /gpio21 wake-up signal input in ? serial clock line scl0/sdata1_bs1/gpio41 scl1/txd1/gpio10 clock signal for dual i 2 c module operation in/out ? serial data line sda0/sdata3/gpio42 sda1/rxd1/gpio44 serial data port for second i 2 c module operation in/out ? receive data sda1/rxd1/gpio44 rxd0/gpio46 ef/rxd2/gpio6 receive serial data input for uart in ? transmit data scl1/txd1/gpio10 txd0/gpio45 xtrim/txd2/gpio0 transmit serial data output for uart out ? request-to-send ddata3/rts0 /gpio4 ddata1/rts1 /sdata2_bs2/gpio2 signals sent from uart0/1 that it is ready to receive data out ? clear-to-send ddata2/cts 0 /gpio3 ddata0/cts1 /sdata0_sdio1/gpio1 signals sent to uart0/1 that data can be transmitted to peripheral in ? timer output sdatao1/tout0/gpio18 cap ability of output waveform or pulse generation out ? iec958 inputs ebuin1/gpio36 ebuin2/sclkout/gpio13 ebuin3/cmd_sdio2/gpio14 qspics0/ebuin4/gpio15 audio interfaces to iec958 inputs in ? iec958 outputs ebuout1/gpio37 qspics1/ebuout2/gpio16 audio interfaces to iec958 outputs out ? serial data in sdatai1/gpio17 sdatai3/gpio8 audio interfaces to serial data inputs in ? table 3. MCF5253 signal index (continued) signal name mnemonic function input/ output reset state
signal description MCF5253 coldfire processor data sheet: technical data, rev. 2 8 freescale semiconductor serial data out sdatao1/tout0/gpio18 sdatao2/gpio34 audio interfaces to serial data outputs in/out out ? word clock lrck1/gpio19 lrck2/gpio23 lrck3/audioclock/gpio43 audio interfaces to serial word clocks in/out ? bit clock sclk1/gpio20 sclk2/gpio22 sclk3/gpio35 audio interfaces to serial bit clocks in/out ? serial input ef/rxd2/gpio6 error flag serial in in/out ? serial input cflg/gpio5 c-flag serial in in/out ? subcode clock rck/qspidin/qspidout/ gpio26 audio interfaces to subcode clock in/out ? subcode sync qspidout/sfsy/gpio27 audi o interfaces to subcode sync in/out ? subcode data qspiclk/subr/gpio25 audio interfaces to subcode data in/out ? clock frequency trim xtrim/txd2/gpio0 clock trim control out ? audio clocks out mclk1/gpio11 qspics2/mclk2/gpio24 dac output clocks out ? audio clock in lrck3/audioclock/gpio43 optional audio clock input ? memorystick/ securedigital interface ebuin3/cmd_sdio2/gpio14 secure digital command lane? memorystick interface 2 data i/o in/out ? ebuin2/sclkout/gpio13 clock out for both memorystick interfaces and for secure digital in/out ? ddata0/cts1 /sdata0_sdio1/gpio1 securedigital serial data bit 0? memorystick interface 1 data i/o in/out ? scl0/sdata1_bs1/gpio41 securedigital serial data bit 1? memorystick interface 1 strobe in/out ? ddata1/rts1 /sdata2_bs2/gpio2 securedigital serial data bit 2? memorystick interface 2 strobe reset output signal in/out ? sda0/sdata3/gpio42 securedigital serial data bit 3 in/out ? table 3. MCF5253 signal index (continued) signal name mnemonic function input/ output reset state
signal description MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 9 at attachment interface (ide interface) ata_diow ata write strobe signal out ? ata_dior ata read strobe signal out ? ata_iordy ata i/o ready input in ? ata_dmarq ata dma request in ? ata_dmack ata dma acknowledge out ? ata_intrq ata interrupt request in ? ata_cs0 ata chip select 0 out ? ata_cs1 ata chip select 1 out ? ata_a[2:0] 3-bit ata address bus out ? ata_d[15:0] 16-bit ata data bus in/out ? can interface can0_tx can 0 transmit out ? can0_rx can 0 receive in ? can1_tx can 1 transmit out ? can1_rx can 1 receive in ? usb phy interface usbvbus usb vbus input in ? usbid usb id input in ? usbres usb current programming resistor pin analog ? usbdn usb dm signalling line in/out ? usbdp usb dp signalling line in/out ? usb oscillator usb_crin usb_crout connections for usb oscillator crystal (24 mhz) in out ? rtc oscillator rtc_crin rtccrout connections for real-time clock crystal (32.768 khz) in out ? ad in adin0/gpi52 adin1/gpi53 adin2/gpi54 adin3/gpi55 adin4/gpi56 adin5/gpi57 analog-to-digital converter input signals in ? ad out adref adout/sclk4/gpio58 analog-to-digital converter output signal?connects to adref via integrator network. in/out ? qspi clock qspiclk/subr/gpio25 qspi clock signal in/out ? qspi data in rck/qspi din/qspidout/gpio26 q spi data input in/out ? table 3. MCF5253 signal index (continued) signal name mnemonic function input/ output reset state
signal description MCF5253 coldfire processor data sheet: technical data, rev. 2 10 freescale semiconductor qspi data out rck/qspi din/qspidout/gpio26 qspidout/s fsy/gpio27 qspi data out in/out ? qspi chip selects q spics0/ebuin4/gpio15 qspics1/ebuout2/gpio16 qspics2/mclk2/gpio24 cs1 /qspics3/gpio28 qspi chip selects in/out ? system oscillator in crin system input in ? system oscillator out crout system output out ? reset in rsti processor reset input in ? freescale test mode test[2:0] test pins. in ? linear regulator output linout outp ut of 1.2 v to supply core out ? linear regulator input linin input, typically i/o supply (3.3v) in ? linear regulator ground lingnd ? high impedance hi_z assertion tri-states output signal pins in debug data ddata0/cts1 /sdata0_sdio1/gpio1 ddata1/rts1 /sdata2_bs2/gpio2 ddata2/cts0 /gpio3 ddata3/rts0 /gpio4 display of captured processor data and break-point statuses in/out hi-z processor status pst0/gpio50 pst1/gpio49 pst2/intmon2/gpio48 pst3/intmon1/gpio47 indication of internal processor status. in/out hi-z processor clock pstclk/gpio51 processor clock output out ? test clock tck clock signal for ieee 1149.1a jtag in ? test reset/ development serial clock dsclk/trst multiplexed signal that is asynchronous reset for jtag controller. also, clock input for debug module. in ? test mode select/break point tms/bkpt multiplexed signal that is test mode select in jtag mode and a hardware break-point in debug mode in ? test data input/ development serial input tdi/dsi multiplexed serial input for the jtag or background debug module. in ? test data output/development serial output tdo/dso multiplexed serial output for the jtag or background debug module out ? table 3. MCF5253 signal index (continued) signal name mnemonic function input/ output reset state
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 11 4 electrical specifications table 4 through table 9 provide the electrical char acteristics for the MCF5253 processor. the remaining figures and tables in this section provide the timi ng diagrams and the timing parameters for the MCF5253 processor. table 4 provides the maximum rating parameters for the MCF5253 processor. table 5 provides the recommended operating te mperatures for the MCF5253 processor. table 6 provides the recommended operating s upply voltages for the MCF5253 processor. table 4. maximum ratings rating symbol value units supply core voltage v cc -0.5 to +2.5 v maximum core operating voltage v cc +1.32 v minimum core operating voltage v cc +1.08 v supply i/o voltage v cc -0.5 to +4.6 v maximum i/o operating voltage v cc +3.6 v minimum i/o operating voltage v cc +3.0 v input voltage v in ?0.5 to +6.0 v storage temperature range t stg ?65 to +150 o c table 5. operating temperature characteristic symbol value units maximum operating ambient temperature t amax +70 1 1 this published maximum operating ambient temperature s hould be used only as a system design guideline. all device operating parameters are guaranteed only when the junction temperature does not exceed 86.5 o c. o c minimum operating ambient temperature t amin -20 o c table 6. recommended operating supply voltages pin name min typ max unit corevdd 1.08 1.2 1.32 v padvdd 3.0 3.3 3.6 v advdd 3.0 3.3 3.6 v adgnd ? gnd ? v oscpadvdd 3.0 3.3 3.6 v oscpadgnd ? gnd ? v usbvdd ? 3.3 ? v usbvddp ? 1.2 ? v
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 12 freescale semiconductor table 7 provides the operating paramete rs for the linear regulator. note a pmos regulator is used as a current source in this linear regulator, so a 10 f capacitor (esr 0... 5 ohm) is needed on the output pin (linout) to integrate the current. typically, this requires the use of a tantalum type capacitor. table 8 provides the operating parameters for the adc dc electrical characteristics. table 9 provides the dc electrical speci fications for the digital pins. usbgnd ? gnd ? v rtcvdda 3.0 ? 4.2 v rtcvssa ? gnd ? v pllcorevdd 1.08 1.2 1.32 v pllcoregnd ? gnd ? v linin 3.0 3.3 3.6 v gnd ? gnd ? v table 7. linear regulator operating parameters characteristic symbol min typ max units input voltage (linin) vin 3.0 3.3 3.6 v output voltage (linout) vout 1.08 1.2 1.32 v output current iout ? 100 ? ma power dissipation pd ? ? 500 mw load regulation 10% iout 90% iout ? ? 50 60 mv power supply rejection psrr ? 40 ? db table 8. operating parameters for adc dc electrical characteristics characteristic symbol min typ max units operation voltage range for adc advdd 3 ? 3.6 v common mode rejection cmr 0 ? advdd?1.1 v reference voltage (external) adref 0 ? advdd?1.1 v input offset voltage v offset ?10 ? mv input hysteresis (adinx = advdd/2) v hyst 0.73 0.78 0.85 mv adc input linear operating range adinx 0 ? advdd?1.1 v table 6. recommended operating supply voltages (continued) pin name min typ max unit
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 13 table 9. dc electrical specifications (i/o vcc = 3.3 vdc + 0.3 vdc) characteristic symbol min max units operation voltage range for i/o v cc 3.0 3.6 v input high voltage v ih 25.5 v input low voltage v il -0.3 0.8 v input leakage current @ 0.0 v/3.3 v during normal operation i in ? 1 a hi-impedance (three-sta te) leakage current @ 0.0 v/3.3 v during normal operation i tsi ? 1 a output high voltage i oh = 11.9 ma 1 , 6.3 ma 2 ,3.1 ma 3 1 8.0 ma: scl0, sda0, scl1, sda1 , pst[3:0], ddata[3:0 ], tdso, rw, ata_rst , mclk1, qspics2_mclk2 2 4.0 ma: bufenb1 , bufenb2 , ebuout1, sclkout, cmdsdio, ide _ dior , ide _ diow , tout0, rts [1:0], txd[1:0], sclk[4:1], lrck[4:1], sdatao1, sdatao2, qspiclk, qspics0, qspics1_ebuout2, qspics3, qspidout, rck, xtrim, a[8:1], ata_cs0, ata_cs1, ata_a[2:0] 3 2.0 ma: tms/bkpt , dsi/tdi, trst /dsclk v oh 2.4 ? v output low voltage i ol = 7.1m a 1 , 3.5 ma 2 , 1.8 ma 3 v ol ?0.4 v schmitt trigger low to high threshold point 4 4 sclk[4:1], scl0, scl1, sda0, sda1, ata_dmarq, ata_in trq, ata_iordy v t+ 1.67 1.79 v schmitt trigger high to low threshold point 4 v t- 1.01 1.15 v load capacitance: d[31:16], sclk[4:1], sclkout, ebuout[2:1 ], lrck[3:1], sdatao[2:1], cflg, ef, ide _d ior , ide _d iow , ide_i ordy , mclk1, mclk2 c l ?50pf load capacitance: a[24:9], ata_cs0, ata_cs 1, ata_a[2:0], ata_dior, ata_diow, ata_dmack, ata_d[15:0], sdatai[3,1] c l 15 40 pf load capacitance: a[8:1], adout, ata_rst bclk, bclke, sdcas , sdras , sdldqm , sd c s0 , sdudqm , sdwe , bufenb [2:1], can0_tx, can1_tx, ebuin1, rxd[2:0] c l ?30pf load capacitance: sda0, sda1, scl0, scl1, cmd_sdio2, sd ata2_bs2, sdata1_bs1, sdata0_sdio1, cs0 /c s4 , cs1 , oe , rw, ta, txd[2:0], xtrim, tdo/ dso, rck, sfsy, subr, sdata3, tout0, qspid_out, qspics[3:0], qspiclk, gpio[6:5] c l ?20pf load capacitance: ddata[3:0], pst [3:0], pstclk c l ?15pf capacitance 5 , v in = 0 v, f = 1 mhz 5 capacitance c in is periodically sampled rather than 100% tested. c in ?6pf
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 14 freescale semiconductor figure 2 and table 10 provide the clock timing di agram and timing parameters. figure 2. clock timing definition note signals shown in figure 2 are in relation to the sysclk clock. no relationship between signals is implied or intended. 4.1 sdram bus timing the sdram bus is a synchronous bus. propagation dela ys, set-up times and hold times with respect to the sdram clock bclk are shown in figure 3 and the parameters provided in table 11 . when bclk clock is not active, sdram interface is not valid and the external bus cannot be used. table 10. clock timing parameters id characteristic 140 mhz cpu units min max ? crin frequency with extern al oscillator 5.00 33.86 mhz ? crin frequency with internal oscillator 5 16.94 mhz c5 pstclk cycle time 7 ? ns c6 pstclk duty cycle 40 60 % c7 bclk cycle time 14.0 ? ns c8 bclk duty cycle 35 65 % crin c5 c7 c8 c8 c6 c6 pstclk bclk
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 15 figure 3. sdram bus timing diagram 4.2 spdif timing the sony/philips digital in terface (spdif) timing para meters are provided in table 12 . spdif timing is totally asynchronous, therefore there is no need for relationshi p with the clock. table 12 shows the differences between high-low and low-high pr opagation delay which is called the skew. table 11. sdram bus timing parameters id characteristic timing to 50% points maximum units 30 pf load 40 pf load 50 pf load d1 propagation delay bclk rising to data valid 7.88 8.8 9.6 ns d2 propagation delay bclk rising to bclke, sdldqm , sdudqm , sdwe , sdcs0 , sdras , sdcas valid 8.7 ? ? ns d3 propagation delay bclk rising to a[24:9] valid 8.3 9.2 ? ns d4 set-up time data valid to bclk rising 0 0 0 ns d5 hold time bclk rising to data valid 0.7 0.7 0.7 ns bclk data (write) bclke, sdxdqm, sdwe , sdcs0 , sdras, sdcas a[24:9] data (read) d1 d2 d3 d4 d5
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 16 freescale semiconductor 4.3 serial audio interface timing the serial audio interface fully comp lies with the industry st andard philips iis (inter ic serial audio bus) timings. 4.4 ddata/pst/pstclk debug interface table 13 provides the timing parameters. 4.5 bdm and jtag timing table 14 provides the bdm timing parameters. figure 4 provides the jtag timing diagram and table 15 provides the jtag timing parameters. table 12. spdif propagation skew and transition parameters characteristic pin load prop delay maximum skew 1 maximum 1 skew value does not include the skew introduced by different rise and fall times. transition 2 rise maximum 2 transition times between 10% vdd and 90% vdd. transition fall maximum units ebuin1, ebuin2, ebuin3, ebuin4: asynchronous inputs, no specs apply ??0.7 ? ?ns ebuout1, ebuout2 output 40 pf ? 1.5 24.2 31.3 ns ebuout1, ebuout2 output 20 pf ? 1.5 13.6 18.0 ns table 13. ddata/pst/pstclk deb ug interface timing parameters characteristic pin load min max units pstclk clock rise edge to ddata/pstdata 1 invalid 1 note that output data may go invalid before rising edge of the clock. to clock data in reliably, you need to sample data, for example, 2 ns before rising edge of clock. 15 pf ?1.0 ? ns pstclk clock rise edge to ddata/pstdata 2 valid 2 timing figure given takes 50% margin for noise and uncertainty on pin capacitance. simulated clock-to-data, not taking noise effects into account is 2.7 ns. 15 pf ? 4.0 ns table 14. bdm interface timing parameters characteristic min max units clock period for dsclk clock ? 5t 1 1 t denotes the cpu clock period. e.g. if the cpu is running at 100 mhz, t = 10 ns ns set-up time dsi, bkpt , to dsclk rising edge 4.0 ? ns hold time dsi, bkpt to dsclk rising edge ? t+ 4.0 ns propagation delay dsclk rising edge to tdo/dso change 3t 4t + 32 ns
electrical specifications MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 17 figure 4. jtag timing diagram table 15. jtag timing parameters id characteristic min max units ? tck frequency of operation 0 10 mhz j1 tck cycle time 100 ? ns j2a tck clock pulse high width 25 ? ns j2b tck clock pulse low width 25 ? ns j3a tck fall time (v ih =2.4 v to v il =0.5 v) ? 5 ns j3b tck rise time (v il =0.5 v to v ih =2.4 v) ? 5 ns j4 tdi, tms to tck rising (input setup) 8 ? ns j5 tck rising to tdi, tms invalid (hold) 10 ? ns j6 boundary scan data valid to tck (setup) 1 ? ns j7 tck to boundary scan data invalid to rising edge (hold) 10 ? ns j8 trst pulse width (asynchronous to clock edges) 12 ? ns j9 tck falling to tdo valid (signal from driven or three-state) ? 15 ns j10 tck falling to tdo high impedance 2 15 ns tdi, tms tck j1 j2a j4 j2b j3a j3b j5 j6 j7 j1 j11 j9 j12 j10 boundary scan data input boundary scan data output trst tdo
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 18 freescale semiconductor 5 package information and pinout this section includes the pin assignment informati on, contact connection diagra m, and the mechanical package drawing. the MCF5253 device is available in the following package: ? 225 mapbga 13 x 13 mm 0.8 mm pitch package as shown in figure 5 . 5.1 pin assignment table 16 defines all the setti ngs of each pad. see figure 6 for the ball map of pin locations and table 18 for the device pin list, sorted by signal identification. j11 tck falling to boundary scan data valid (signal from driven or three-state) ? 15 ns j12 tck falling to boundary scan. data high impedance 1 15 ns table 16. 225 mapbga pin assignment name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes address bus a1 o / 2 ma 30 ?? ?? x h 3 ? a2 o / 2 ma 30 ?? ?? x h 2 ? a3 o / 2 ma 30 ?? ?? x h 1 ? a4 o / 2 ma 30 ?? ?? x h 5 ? a5 o / 2 ma 30 ?? ?? x g 1 ? a6 o / 2 ma 30 ?? ?? x g 3 ? a7 o / 2 ma 30 ?? ?? x g 2 ? a8 o / 2 ma 30 ?? ?? x h 4 ? a9 o / 8 ma 30 ?? ?? x h 6 ? a10 o / 8 ma 30 ?? ?? x f 2 ? a11 o / 8 ma 30 ?? ?? x g 5 ? a12 o / 8 ma 30 ?? ?? x f 3 ? a13 o / 8 ma 30 ?? ?? x f 1 ? a14 o / 8 ma 30 ?? ?? x e 1 ? a15 o / 8 ma 30 ?? ?? x g 4 ? a16 o / 8 ma 30 ?? ?? x e 2 ? a17 o / 8 ma 30 ?? ?? x f 4 ? a18 o / 8 ma 30 ?? ?? x e 3 ? a19 o / 8 ma 30 ?? ?? x f 5 ? a20/a24 o / 8 ma 30 a20 a24 31 ? x f 6 audio clock select: 1-lrck3 pin; 0-crin pin a21 o / 8 ma 30 ?? ?? x d 3 ? a22 o / 8 ma 30 ?? ?? x d 1 ? a23/gpo54 o / 8 ma 30 a23 ?? o54 x d 2 boot mode select:1-memory connected to cs0 ; 0-internal boot rom table 15. jtag timing parameters (continued) id characteristic min max units
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 19 data bus d16 io / 8 ma 40 ?? ?? hi_z c 1 ? d17 io / 8 ma 40 ?? ?? hi_z e 4 ? d18 io / 8 ma 40 ?? ?? hi_z e 5 ? d19 io / 8 ma 40 ?? ?? hi_z b 1 ? d20 io / 8 ma 40 ?? ?? hi_z c 2 ? d21 io / 8 ma 40 ?? ?? hi_z d 4 ? d22 io / 8 ma 40 ?? ?? hi_z c 3 ? d23 io / 8 ma 40 ?? ?? hi_z b 2 ? d24 io / 8 ma 40 ?? ?? hi_z a 2 ? d25 io / 8 ma 40 ?? ?? hi_z b 3 ? d26 io / 8 ma 40 ?? ?? hi_z a 3 ? d27 io / 8 ma 40 ?? ?? hi_z c 4 ? d28 io / 8 ma 40 ?? ?? hi_z b 4 ? d29 io / 8 ma 40 ?? ?? hi_z d 5 ? d30 io / 8 ma 40 ?? ?? hi_z a 4 ? d31 io / 8 ma 40 ?? ?? hi_z c 5 ? bus control oe o / 4 ma 30 ?? ?? negated r 3 ? rw o / 4 ma 30 ?? ?? h j 4 ? ta /gpio12 io / 2 ma 30 ta ?? io12 ? n 5 ? bufenb1 /gpio29 io / 2 ma 30 bufenb1 ?? io29 ? p 5 ? bufenb2 /gpio30 io / 2 ma 30 bufenb2 ?? io30 ? k 6 ? ide_dior /gpio31 io / 2 ma 30 ide _ dior ?? io31 ? m 5 controlled by cs2 registers ide_diow /gpio32 io / 2 ma 30 ide _ diow ?? io32 ? p 4 controlled by cs2 registers ide_iordy /gpio33 io / 2 ma 30 ide _ iordy ?? io33 ? r 4 ? chip selects cs0 /cs4 o / 4 ma 30 cs0 cs4 ?? negated j 3 boot mode select:1-cs0 ; 0-cs4 cs1 /qspics3/ gpio28 io / 2 ma 30 cs1 qspics3 25 io28 negated m 7 ? sdram controller bclk/gpio40 io / 8 ma 15 bclk ?? io40 ? b 5 ? bclke/gpio63 io / 8 ma 20 bclke ?? io63 ? e 6 ? sdldqm /gpo52 o / 8 ma 20 sdldqm ?? o52 ? c 6 ? sdudqm /gpo53 o / 8 ma 20 sdudqm ?? o53 ? a 5 ? sdwe /gpio38 io / 8 ma 20 sdwe ?? io38 negated c 7 ? sdcs0 /gpio60 io / 8 ma 20 sdcs0 ?? io60 negated b 6 ? sdras /gpio59 io / 8 ma 20 sdras ?? io59 negated a 6 ? sdcas /gpio39 io / 8 ma 20 sdcas ?? io39 negated d 6 ? ata interface ata_a0 o / 2 ma 40 ?? ??? a 8 ? ata_a1 o / 2 ma 40 ?? ??? b 7 ? ata_a2 o / 2 ma 40 ?? ??? b 8 ? ata_d0 io / 8 ma 40 ?? ??? b 9 ? ata_d1 io / 8 ma 40 ?? ??? a 9 ? table 16. 225 mapbga pin assignment (continued) name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 20 freescale semiconductor ata_d2 io / 8 ma 40 ?? ??? f 8 ? ata_d3 io / 8 ma 40 ?? ??? f 9 ? ata_d4 io / 8 ma 40 ?? ??? b 1 0 ? ata_d5 io / 8 ma 40 ?? ??? c 1 0 ? ata_d6 io / 8 ma 40 ?? ??? a 1 0 ? ata_d7 io / 8 ma 40 ?? ??? d 1 0 ? ata_d8 io / 8 ma 40 ?? ??? d 1 1 ? ata_d9 io / 8 ma 40 ?? ??? b 1 1 ? ata _ d 1 0 i o / 8 m a 4 0 ?? ??? c 1 1 ? ata _ d 1 1 i o / 8 m a 4 0 ?? ??? a 1 1 ? ata _ d 1 2 i o / 8 m a 4 0 ?? ??? a 1 2 ? ata _ d 1 3 i o / 8 m a 4 0 ?? ??? e 1 1 ? ata _ d 1 4 i o / 8 m a 4 0 ?? ??? b 1 2 ? ata _ d 1 5 i o / 8 m a 4 0 ?? ??? d 1 2 ? ata_cs0 o / 2 ma 40 ?? ??? c 9 ? ata_cs1 o / 2 ma 40 ?? ??? d 9 ? ata_dior o / 8 ma 40 ?? ??? b 1 5 ? ata _ d i ow o / 8 m a 4 0 ?? ??? a 1 3 ? ata _ i o r dy i ?? ? ??? d 7 ? ata _ i n t r q i ?? ? ??? d 8 ? ata_dmarq i ?? ? ??? a 7 ? ata_dmack o / 8 ma 40 ?? ??? c 1 2 ? ata _ r s t o / 2 ma 40 ?? ??? c 8 ? clock generation crin ??? ? ??? m 3 main processor clock input crout ??? ? ??? n 2 main processor clock output rtc_crin a ?? ? ??? j 1 real time clock (32.768 khz) input rtccrout a ?? ? ??? k 2 real time clock (32.768 khz) output usb_crin a ?? ? ??? l 1 4 usb clock (24 mhz) input usb_crout a ?? ? ??? l 1 5 usb clock (24 mhz) output xtrim/txd2/gpio0 io / 2 ma 30 xtrim txd2 0 io0 ? r 6 interrupt capable input jtag/bdm/test tdo/dso o / 4 ma 30 ?? ??? g 1 3 see test0 description tdi/dsi i ?? ? ??? f 1 5 see test0 description tms/bkpt i ?? ? ??? f 1 2 see test0 description tck i ?? ? ??? f 1 3 ? trst /dsclk i ?? ? ??? f 1 4 see test0 description hi_z i ?? ? ??? b 1 3 for normal operation tie this pin high pstclk/gpio51 io / 8 ma 30 pstclk ?? io51 ? g 1 4 ? pst0/gpio50 io / 4 ma 30 pst0 ?? io50 hi_z g 1 5 ? pst1/gpio49 io / 4 ma 30 pst1 ?? io49 hi_z g 1 2 ? pst2/intmon2/ gpio48 io / 4 ma 30 pst2 intmon2 17 io48 hi_z h 1 4 ? pst3/intmon1/ gpio47 io / 4 ma 30 pst3 intmon1 18 io47 hi_z h 1 3 ? table 16. 225 mapbga pin assignment (continued) name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 21 ddata0/cts1 / sdata0_sdio1/gpio1 io / 4 ma 30 ddata0 cts1 /sdata 0_sdio1 14,13 io1 hi_z k 1 0 interrupt capable input ddata1/rts1 / sdata2_bs2/gpio2 io / 4 ma 30 ddata1 rts1 /sdata 2_bs2 24,23 io2 hi_z r 1 1 interrupt capable input ddata2/cts0 /gpio3 io / 4 ma 30 ddata2 cts0 22 io3 hi_z j 1 4 interrupt capable input ddata3/rts0 /gpio4 io / 4 ma 30 ddata3 rts0 21 io4 hi_z j 1 2 interrupt capable input test0 i ?? ? ??? f 1 1 bdm/jtag select: 1-bdm; 0-jtag test1 i ?? ? ??? g 1 0 for normal operation, tie this pin low. test2 i ?? ? ??? h 1 0 for normal operation, tie this pin low. reset/wake-up rsti i ?? ? ??? e 1 5 ? wakeup /gpio21 io / 2 ma 30 wakeup ?? io21 ? r 5 ? usb usbdn a ?? ? ??? n 1 5 ? usbdp a ?? ? ??? m 1 5 ? usbid i ?? ? ??? m 1 1 ? usbvbus a ?? ? ??? n 1 4 ? usbres a ?? ? ??? m 1 4 ? testout 1 o ?? ? ??? p 1 3 ? nc ??? ? ??? r 1 4 ? audio interface sdatai1/gpio17 io / 2 ma 30 sdatai1 ?? io17 ? n 9 ? sdatao1/tout0/ gpio18 io / 2 ma 30 sdatao1 tout0 8 io18 ? r 8 ? sclk1/gpio20 io / 2 ma 30 sclk1 ?? io20 ? k 8 ? lrck1/gpio19 io / 2 ma 30 lrck1 ?? io19 ? p 8 ? sdatao2/gpio34 io / 2 ma 30 sdatao2 ?? io34 ? d 1 5 ? sclk2/gpio22 io / 2 ma 30 sclk2 ?? io22 ? e 1 3 ? lrck2/gpio23 io / 2 ma 30 lrck2 ?? io23 ? e 1 4 ? sdatai3/gpio8 io / 2 ma 30 sdatai3 ?? io8 ? n 1 0 ? sclk3/gpio35 io / 2 ma 30 sclk3 ?? io35 ? r 1 0 ? lrck3/audioclk/ gpio43 io / 2 ma 30 lrck3 audioclk ? io43 ? m 1 0 see a20/a24 description ebuin1/gpio36 io / 2 ma 30 ebuin1 ?? io36 ? n 6 ? ebuin2/sclkout/ gpio13 io / 2 ma 30 ebuin2 sclkout 16 io13 ? m 6 ? ebuin3/ cmd_sdio2/gpio14 io / 2 ma 30 ebuin3 cmdsdio2 15 io14 ? k 7 ? qspics0/ebuin4/ gpio15 io / 2 ma 30 qspics0 ebuin4 30 io15 ? r 7 ? ebuout1/gpio37 io / 2 ma 30 ebuout1 ?? io37 ? p 6 ? qspics1/ ebuout2/gpio16 io / 2 ma 30 qspics1 ebuout2 29 io16 ? n 8 ? cflg/gpio5 io / 2 ma 30 cflg ?? io5 ? m 9 interrupt capable input ef/rxd2/gpio6 io / 2 ma 30 ef rxd2 ? io6 ? r 9 interrupt capable input table 16. 225 mapbga pin assignment (continued) name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 22 freescale semiconductor mclk1/gpio11 io / 4 ma 30 mclk1 ?? io11 ? d 1 4 ? qspics2/mclk2/ gpio24 io / 4 ma 30 qspics2 mclk2 28 io24 ? p 9 ? analog-to-digital converter adin0/gpi52 a ? adin0 ?? i52 ? k 3 ? adin1/gpi53 a ? adin1 ?? i53 ? l 1 ? adin2/gpi54 a ? adin2 ?? i54 ? l 2 ? adin3/gpi55 a ? adin3 ?? i55 ? l 3 ? adin4/gpi56 a ? adin4 ?? i56 ? m 1 ? adin5/gpi57 a ? adin5 ?? i57 ? j 6 ? adref a ?? ? ??? m 2 ? adout/sclk4/ gpio58 io / 2 ma 30 adout sclk4 9 io58 ? j 5 ? flexcan can0_tx o / 8 ma 30 ?? ??? c 1 5 ? can0_rx i ?? ? ??? d 1 3 ? can1_tx o / 8 ma 30 ?? ??? c 1 4 ? can1_rx i ?? ? ??? e 1 2 ? qspi qspiclk/subr/ gpio25 io / 2 ma 30 qspiclk subr 27 io25 ? p 7 ? rck/qspidin/ qspidout/gpio26 io / 2 ma 30 rck qspidin/ qspidout 26 io26 ? n 7 ? qspidout/sfsy/ gpio27 io / 2 ma 30 qspidout sfsy 10 io27 ? m 8 ? i 2 c sda0/sdata3/ gpio42 io / 4 ma 30 sda0 sdata3 11 io42 ? k 9 ? scl0/sdata1_bs1/ gpio41 io / 4 ma 30 scl0 sdata1_bs1 12 io41 ? p 1 0 ? sda1/rxd1/gpio44 io / 4 ma 30 sda1 rxd1 19 io44 ? j 1 5 ? scl1/txd1/gpio10 io / 4 ma 30 scl1 txd1 20 io10 ? j 1 3 ? uart txd0/gpio45 io / 2 ma 30 txd0 ?? io45 ? h 1 2 ? rxd0/gpio46 io / 2 ma 30 rxd0 ?? io46 ? h 1 5 ? power/ground pins linin ??? ? ??? a 1 4 3.3 volt supply required linout ??? ? ??? b 1 4 1.2 volt output (approx 50% efficient) lingnd ??? ? ??? c 1 3 ? pllcorevdd (3 balls) ??? ? ??? s e e n ot e s 1.2 volt supply required (m4, n3, p2) pllcoregnd (3 balls) ??? ? ??? s e e n ot e s n4,p3,r2 usbvdd (2 balls) ??? ? ??? s e e n ot e s 3.3 volt supply required (l13, m13) usbvddp ??? ? ??? l 1 2 1.2 volt supply required table 16. 225 mapbga pin assignment (continued) name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 23 usbgnd (3 balls) ??? ? ??? s e e n ot e s k11, l11, m12 oscpadvdd ??? ? ??? n 1 3.3 volt supply required oscpadgnd ??? ? ??? p 1 ? rtc_vdda ??? ? ??? j 2 3.3 volt supply required rtcvssa ??? ? ??? k 1 ? advdd ??? ? ??? k 4 3.3 volt supply required adgnd ??? ? ??? l 4 ? padvdd (10 balls) ??? ? ??? s e e n ot e s 3.3 volt supply required (e7, e9, f10, h8, h11, k5, l6, l8, l10, r13) corevdd (4 balls) ??? ? ??? s e e n ot e s 1.2 volt supply required (g8, h7, h9, j8) corevss/padvss (18 balls) 2 ??? ? ??? s e e n ot e s a1, a15, e8, e10, f7, g6, g7, g9, g11, j7, j9, j10, j11, l5, l7, l9, r1, r15 1 for test purposes only. leave ball as open circuit. 2 these pads are listed as ?gnd? in the ball map and the rest of the tables. table 16. 225 mapbga pin assignment (continued) name drive type/ strength load (pf) 1st function 2nd function pinconfig register bit gp pin reset notes
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 24 freescale semiconductor 5.2 package drawing figure 5 shows the package outline di agram for the MCF5253 processor. figure 5. MCF5253 package drawing bottom view side view top view notes: 1. all dimensions in millimeters. 2. dimensioning and toler ancing per asme y14. 5m?1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crown of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package.
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 25 5.2.1 mapbga pinout figure 6 shows the MCF5253 ball map of pad locations. figure 6. MCF5253 ball map 123456789101112131415 a gnd d24 d26 d30 sdudqm / gpo53 sdras / gpio59 ata_dmar q ata_a0 ata_d1 ata_d6 ata_d11 ata_d12 ata_diow linin gnd a b d19 d23 d25 d28 bclk/ gpio40 sdcs0 / gpio60 ata_a1 ata_a2 ata_d0 ata_d4 ata_d9 ata_d14 hi_z linout ata_dior b c d16 d20 d22 d27 d31 sdldqm / gpo52 sdwe / gpio38 ata_rst ata_cs0 ata_d5 ata_d10 ata _ d m ac k lingnd can1_tx can0_tx c d a22a23/gpo54a21 d21 d29 sdcas / gpio39 ata_iordy ata_intrq ata_cs1 ata_d7 ata_d8 ata_d15 can0_rx mclk1/ gpio11 sdatao2/ gpio34 d e a14 a16 a18 d17 d18 bclke/ gpio63 pa dv d d gnd pa dv d d gnd ata_d13 can1_rx sclk2/ gpio22 lrck2/ gpio23 rsti e f a13 a10 a12 a17 a19 a20/a24 g n d ata _ d 2 ata _ d 3 padvdd test0 tms/bkpt tck trst / dsclk tdi/dsi f g a5 a7 a6 a15 a11 gnd gnd corevdd gnd test1 gnd pst1/ gpio49 tdo/dso pstclk/ gpio51 pst0/ gpio50 g h a3 a2 a1 a8 a4 a9 corevdd pa dv d d corevdd test2 pa dv d d txd0/ gpio45 pst3/ intmon1/ gpio47 pst2/ intmon2/ gpio48 rxd0/ gpio46 h j rtc_crin rtc_vdda cs0 /cs4 rw adout/ sclk4/ gpio58 adin5/ gpi57 gnd corevdd gnd gnd gnd ddata3/ rts0 / gpio4 scl1/txd1/ gpio10 ddata2/ cts0 / gpio3 sda1/rxd1 /gpio44 j k rtcvssa rtccrout adin0/ gpi52 advdd pa dv d d bufenb2 / gpio30 ebuin3/cm d_sdio2/ gpio14 sclk1/ gpio20 sda0/ sdata3/ gpio42 ddata0/ cts1 /sdat a0_sdio1/ gpio1 usbgnd n/c n/c n/c n/c k l adin1/ gpi53 adin2/ gpi54 adin3/ gpi55 adgnd gnd pa dv d d gnd pa dv d d gnd pa dv d d usbgnd usbvddp usbvdd usb_crin usb_crou t l m adin4/ gpi56 adref crin pllcore vdd ide_dior / gpio31 ebuin2/ sclkout/ gpio13 cs1 / qspics3/ gpio28 qspidout/ sfsy/ gpio27 cflg/ gpio5 lrck3/ audclk/ gpio43 usbid usbgnd usbvdd usbres usbdp m n oscpad vdd crout pllcore vdd pllcore gnd ta /gpio12 ebuin1/ gpio36 rck/qspid in/qspido ut/gpio26 qspics1/ ebuout2/ gpio16 sdatai1/ gpio17 sdatai3/ gpio8 n/c n/c n/c usbvbus usbdn n p oscpad gnd pllcore vdd pllcore gnd ide_diow / gpio32 bufenb1 / gpio29 ebuout1/ gpio37 qspiclk/ subr/ gpio25 lrck1/ gpio19 qspics2/ mclk2/ gpio24 scl0/sdat a1_bs1/ gpio41 n/c n/c testout n/c n/c p r gnd pllcore gnd oe ide_iordy / gpio33 wakeup / gpio21 xtrim/ txd2/ gpio0 qspics0/ ebuin4/ gpio15 sdatao1/ tout0/ gpio18 ef/rxd2/ gpio6 sclk3/ gpio35 ddata1/rt s1 /sdata2 _bs2/ gpio2 n/c padvdd nc gnd r 123456789101112131415
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 26 freescale semiconductor table 17 shows the signal color and signal name legend. table 18 shows the device pin list, so rted by signal identification. 3 table 17. signal color/name legend color name none signal name as listed gnd pa dv d d corevdd usbgnd table 18. MCF5253 13 x 13 bga (225 signal id by pad grid location) signal id pad location a1 h03 a10 f02 a11 g05 a12 f03 a13 f01 a14 e01 a15 g04 a16 e02 a17 f04 a18 e03 a19 f05 a2 h02 a20/a24 f06 a21 d03 a22 d01 a23/gpo54 d02 a3 h01 a4 h05 a5 g01 a6 g03 a7 g02 a8 h04 a9 h06 adgnd l04 adin0/gpi52 k03 adin1/gpi53 l01 adin2/gpi54 l02 adin3/gpi55 l03 adin4/gpi56 m01 adin5/gpi57 j06 adout/sclk4/gpio58 j05 adref m02 advdd k04
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 27 ata_a0 a08 ata_a1 b07 ata_a2 b08 ata _ c s 0 c 0 9 ata _ c s 1 d 0 9 ata_d0 b09 ata_d1 a09 ata _ d 1 0 c 1 1 ata _ d 1 1 a 1 1 ata _ d 1 2 a 1 2 ata _ d 1 3 e 1 1 ata _ d 1 4 b 1 2 ata _ d 1 5 d 1 2 ata _ d 2 f 0 8 ata _ d 3 f 0 9 ata_d4 b10 ata_d5 c10 ata_d6 a10 ata_d7 d10 ata_d8 d11 ata_d9 b11 ata_dior b15 ata_diow a13 ata _ d m ac k c 1 2 ata_dmarq a07 ata _ i n t r q d 0 8 ata _ i o r dy d 0 7 ata _ r s t c08 bclk/gpio40 b05 bclke/gpio63 e06 bufenb1 /gpio29 p05 bufenb2 /gpio30 k06 can0_rx d13 can0_tx c15 can1_rx e12 can1_tx c14 cflg/gpio5 m09 corevdd g08 corevdd h07 corevdd h09 corevdd j08 crin m03 crout n02 cs0 /cs4 j03 cs1 /qspics3/gpio28 m07 d16 c01 table 18. MCF5253 13 x 13 bga (225 signal id by pad grid location) (continued) signal id pad location
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 28 freescale semiconductor d17 e04 d18 e05 d19 b01 d20 c02 d21 d04 d22 c03 d23 b02 d24 a02 d25 b03 d26 a03 d27 c04 d28 b04 d29 d05 d30 a04 d31 c05 ddata0/cts1 /sdata0_sdio1/gpio1 k10 ddata1/rts1 /sdata2_bs2/gpio2 r11 ddata2/cts0 /gpio3 j14 ddata3/rts0 /gpio4 j12 ebuin1/gpio36 n06 ebuin2/sclkout/gpio13 m06 ebuin3/cmd_sdio2/gpio14 k07 ebuout1/gpio37 p06 ef/rxd2/gpio6 r09 gnd a01 gnd a15 gnd e08 gnd e10 gnd f07 gnd g06 gnd g07 gnd g09 gnd g11 gnd j07 gnd j09 gnd j10 gnd j11 gnd l05 gnd l07 gnd l09 gnd r01 gnd r15 hi_z b13 ide _d ior /gpio31 m05 ide _d iow /gpio32 p04 ide _i ordy /gpio33 r04 table 18. MCF5253 13 x 13 bga (225 signal id by pad grid location) (continued) signal id pad location
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 29 lingnd c13 linin a14 linout b14 lrck1/gpio19 p08 lrck2/gpio23 e14 lrck3/audioclk/gpio43 m10 mclk1/gpio11 d14 nc r14 oe r03 oscpadgnd p01 oscpadvdd n01 pa dv d d e 0 7 pa dv d d e 0 9 pa dv d d f 1 0 padvdd h08 padvdd h11 pa dv d d k 0 5 pa dv d d l 0 6 pa dv d d l 0 8 pa dv d d l 1 0 padvdd r13 pllavdd m04 pllcoregnd n04 pllcoregnd p03 pllcoregnd r02 pllcorevdd n03 pllcorevdd p02 pst0/gpio50 g15 pst1/gpio49 g12 pst2/intmon2/gpio48 h14 pst3/intmon1/gpio47 h13 pstclk/gpio51 g14 qspiclk/subr/gpio25 p07 qspics0/ebuin4/gpio15 r07 qspics1/ebuout2/gpio16 n08 qspics2/mclk2/gpio24 p09 qspidout/sfsy/gpio27 m08 rck/qspidin/qspidout/gpio26 n07 rsti e15 rtc_crin j01 rtc_vdda j02 rtccrout k02 rtcvssa k01 rw j04 rxd0/gpio46 h15 scl0/sdata1_bs1/gpio41 p10 table 18. MCF5253 13 x 13 bga (225 signal id by pad grid location) (continued) signal id pad location
package information and pinout MCF5253 coldfire processor data sheet: technical data, rev. 2 30 freescale semiconductor scl1/txd1/gpio10 j13 sclk1/gpio20 k08 sclk2/gpio22 e13 sclk3/gpio35 r10 sda0/sdata3/gpio42 k09 sda1/rxd1/gpio44 j15 sdatai1/gpio17 n09 sdatai3/gpio8 n10 sdatao1/tout0/gpio18 r08 sdatao2/gpio34 d15 sdcas /gpio39 d06 sdcs0 /gpio60 b06 sdldqm /gpo52 c06 sdras /gpio59 a06 sdudqm /gpo53 a05 sdwe /gpio38 c07 ta /gpio12 n05 tck f13 tdi/dsi f15 tdo/dso g13 test0 f11 test1 g10 test2 h10 testout p13 tms/bkpt f12 trst /dsclk f14 txd0/gpio45 h12 usb_crin l14 usb_crout l15 usbdn n15 usbdp m15 usbgnd k11 usbgnd l11 usbgnd m12 usbid m11 usbres m14 usbvbus n14 usbvdd l13 usbvdd m13 usbvddp l12 wakeup /gpio21 r05 xtrim/txd2/gpio0 r06 table 18. MCF5253 13 x 13 bga (225 signal id by pad grid location) (continued) signal id pad location
product documentation MCF5253 coldfire processor data sheet: technical data, rev. 2 freescale semiconductor 31 6 product documentation this section includes the related product document ation and references to information posted on freescale?s external web page. this document is labeled as the t ype: data sheet: technical data. de finitions for all freescale document types are available at: http://www.freescale.com. you can also obtain information on the mechanical characterist ics of the MCF5253 integrated microprocessor at http://www.freescale.com/coldfire . the following documents are require d for a complete description of the device and are necessary for proper design: MCF5253 reference manual (order number: MCF5253rm) MCF5253 product brief (order number: MCF5253pb) 6.1 revision history table 19 summarizes revisions to this document. table 19. MCF5253ds revision history rev. no. substantive change(s) 2 first public version.
document number: MCF5253ds rev. 2 03/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2007. all rights reserved.

▲Up To Search▲

Price & Availability of MCF5253

	To Download MCF5253 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .